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general description maxim? redesigned dg406 and dg407 cmos analogmultiplexers now feature guaranteed matching between channels (8 , max) and flatness over the specified sig- nal range (9 , max). these low on-resistance muxes (100 , max) conduct equally well in either direction and feature guaranteed low charge injection (15pc, max). inaddition, these new muxes offer low input off-leakage current over temperature?ess than 5na at +85?. the dg406 is a 1 of 16 multiplexer/demultiplexer and the dg407 is a dual 8-channel multiplexer/demultiplex- er. both muxes operate with a +5v to +30v single sup- ply and with ?.5v to ?0v dual supplies. esd protection is guaranteed to be greater than 2000v per method 3015.7 of mil-std 883. these improved muxes are pin-compatible plug-in upgrades for the industry standard dg406 and dg407. ________________________applications sample-and-hold circuits test equipment guidance and control systems communications systems data-acquisition systems audio signal routing ____________________________features ? ? pin-compatible plug-in upgrade for industrystandard dg406/dg407 ? ? guaranteed matching between channels, 8 (max) ? ? guaranteed on-resistance flatness, 9 (max) ? ? guaranteed low charge injection, 15pc (max) ? ? low on-resistance 100 (max) ? ? input leakage, 5na (max) at +85? ? ? low power consumption, 1.25mw (max) ? ? rail-to-rail signal handling ? ? digital input controls ttl/cmos compatible ? ? esd protection >2000v per method 3015.7 dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers ________________________________________________________________ maxim integrated products 1 cmos decoders/drivers a0 a1 a2 a3 en s1s2 s3 s4 s5 s6 s7 s8 s9 s10s11 s12 s13 s14 s15 s16 d v+ v- gnd dg406 16-channel single-ended multiplexer 2827 26 25 24 23 22 21 12 3 4 5 6 7 8 dv- s8 s7 s6 s5 s4 s3 s2 s1 en a0 a1 a2 v+ n.c.n.c. s16s15 s14 s13 s12 s11 s10 s9 gnd n.c. a3 top view 2019 18 17 9 1011 12 dip/so/tssop dg406 1615 1314 + _________________pin configurations 19-4729; rev 6; 3/10 part dg406 cj+ dg406cwi+ 0? to +70? 0? to +70? temp range pin-package 28 plastic dip28 wide so ordering information continued at end of data sheet. * contact factory for dice specifications. + denotes a lead(pb)-free/rohs-compliant package. dg406c/d 0? to +70? dice* dg406dj+ -40? to +85? 28 plastic dip dg406ewi+ -40? to +85? 28 wide so dg406dn+ -40? to +85? 28 plcc dg406ak+ -55? to +125? 28 cerdip ordering information _______________functional diagrams functional diagrams continued at end of data sheet. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations continued at end of data sheet. dg406eui+ -40? to +85? 28 tssop downloaded from: http:///
dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics?ual supplies(v+ = 15v, v- = -15v, v gnd = 0v, v ah = +2.4v, v al = +0.8v, t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltage referenced to v-) v+ ............................................................................-0.3v, 44v gnd .........................................................................-0.3v, 25v digital inputs, s, d (note 1)....................(v- - 2v) to (v+ + 2v) or 30ma (whichever occurs first) continuous current (any terminal) ......................................30ma peak current, s or d (pulsed at 1ms, 10% duty cycle max) ..........................100ma continuous power dissipation (t a = +70?) 28-pin plastic dip (derate 9.09mw/? above +70?) ..727mw 28-pin wide so (derate 12.50mw/? above +70?) ... 1000mw 28-pin plcc (derate 10.53mw/? above +70 ?) ........842mw 28-pin cerdip (derate 16.67mw/? above +70?)...1333mw 28-pin tssop (derate 12.8mw/? above +70?) ......1025mw operating temperature ranges dg406/dg407c_ ...............................................0? to +70? dg406/dg407d_ ............................................-40? to +85? dg406/dg407ak ..........................................-55? to +125? storage temperature range .............................-65? to +150? lead temperature (excluding dice; soldering, 10s) .......+300? soldering temperature (reflow) plastic dip, wide so, tssop ......................................+260? plcc............................................................................+245? cerdip, dice...............................................................+240? v d = ?0v, v s = ?0v, sequenceeach switch on v d = +10v, v s = ?0v, v en = 0v v d = +10v, v s = ?0v, v en = 0v i s = -1.0ma, v d = ?0v i s = -1.0ma, v d = ?0v (note 4) v d = ?0v, v s = +10v, v en = 0v conditions na -100 +100 i d(on) + i s(on) drain-on leakage current(note 5) -20 +20 -1 +0.02 +1 -200 +200 -40 +40 -1 +0.02 +1 na -100 +100 i d(off) drain-off leakage current(note 5) -20 +20 -1 +0.02 +1 -200 +200 60 100 -40 +40 -1 +0.02 +1 na -50 +50 i s(off) source-off leakage current(note 5) -5 +5 125 r ds(on) drain-source on-resistance 1.5 8 10 ? r ds(on) on-resistance matchingbetween channels units min typ max (note 2) symbol parameter note 1: signals on s_, d_, a0, a1, a2, a3, or en exceeding v+ or v- are clamped by internal diodes. limit forward current to max-imum current ratings. v -15 +15 v analog analog signal range i s = -1.0ma, v d = ?v or 0v 1.8 9 12 r flat on-resistance flatness (note 3) t a = +25? t a = t min to t max t a = +25? t a = t min to t max t a = +25? t a = t min to t max -0.5 +0.01 +0.5 t a = +25? t a = t min to t max t a = +25? t a = t min to t max t a = +25? t a = t min to t max t a = +25? t a = t min to t max t a = +25? t a = t min to t max dg407 dg406 dg407 dg406 c, d a c, d a c, d a c, d a c, d a switch downloaded from: http:///
dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers _______________________________________________________________________________________ 3 electrical characteristics?ual supplies (continued)(v+ = 15v, v- = -15v, v gnd = 0v, v ah = +2.4v, v al = +0.8v, t a = t min to t max , unless otherwise noted.) off-isolation(note 6) db -69 v iso 21 5 q charge injection(note 3) pc 55 150 ns 400 t on(en) enable turn-on time 130 200 ns 10 40 t open break-before-make interval 110 300 ? -1.0 +1.0 i al input current with input voltage low ? -1.0 +1.0 i ah input current with input voltage high ? -10 +10 i- negative supply current -1 +1 ma 1 i+ positive supply current 0.075 0.5 v ?.5 ?0 power-supply range 16 30 ? 75 units min typ max (note 2) symbol parameter crosstalk between channels v ct -92 db logic input capacitance c in 8 pf source-off capacitance c s(off) 8 pf 130 drain-off capacitance c d(off) f = 1mhz,v en = 0.8v, v d = 0v, figure 8 65 pf 140 drain-source oncapacitance c d(on) + c s(on) f = 1mhz,v en = 2.4v, v d = 0v, figure 8 70 pf t a = +25? v en = 0v or 2.4v, v a = 0v t a = +25? v a = 2.4v or 15v t a = +25? t a = t min to t max t a = t min to t max t a = +25? t a = +25? t a = +25? t a = t min to t max t a = +25? t a = +25? t a = +25? t a = t min to t max conditions t a = +25? t a = +25? t a = +25? t a = +25? t a = +25? v en = 0v, r l = 1k , f = 100khz, figure 6 c l = 1.0nf, v s = 0v, r s = 0 , figure 5 figure 3 v en = 2.4v, v a(all) = 0v figure 4 v en = 2.4v, v a(all) = 0v v en = v a = 0v or 5.0v v en = 2.4v, f = 100khz,v gen = 1v p-p , r l = 1k , figure 7 f = 1mhz f = 1mhz,v en = v s = 0v, figure 8 dg406 dg407 dg406 dg407 ns 400 t trans transition time t a = t min to t max figure 2 ns 300 t off(en) enable turn-off time t a = t min to t max figure 3 input supply dynamic downloaded from: http:///
dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers 4 _______________________________________________________________________________________ (note 3) conditions c l = 1.0nf, v s1 = 0v, r s = 0 v al = 0v, v s1 = 5v, figure 3 v al = 0v, v s1 = 5v, figure 3 v s1 = 8v, v s16 = 0v, v a = 0v, figure 2 i s = -1.0ma v d = 3v or 10v pc 21 0 q charge injection(note 3) ns 80 300 t off(en) enable turn-off time(note 3) v 01 2 v analog analog signal range ns 105 600 t on(en) enable turn-on time(note 3) ns 130 450 t trans transition time(note 3) 120 175 r ds(on) drain-source on-resistance units min typ max (note 2) symbol parameter electrical characteristics?ingle supply(v+ = 12v, v- = 0v, v gnd = 0v, v ah = +2.4v, v al = +0.8v, t a = t min to t max , unless otherwise noted.) note 2: the algebraic convention where the most negative value is a minimum and the most positive value a maximum is used inthis data sheet. note 3: guaranteed by design. note 4: ? r on = r on(max) - r on(min) . on-resistance match between channels and flatness are guaranteed only with specified voltages. flatness is defined as the difference between the maximum and minimum value of on-resistance as measured atthe extremes of the specified analog signal range. note 5: leakage parameters are 100% tested at the maximum-rated hot temperature and guaranteed by correlation at +25?. note 6: off-isolation = 20log v d /v s , where v d = output and v s = input to off switch. t a = +25? t a = +25? t a = +25? t a = +25? t a = +25? switch dynamic downloaded from: http:///
dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers _______________________________________________________________________________________ 5 120 140 160 on-resistance vs. v d (dual supplies) 100 dg406/7 toc-01 0 20 40 60 -20 20 -15 15 -10 10 -5 5 0 80 v d (v) 5v 10v 15v 20v r ds (on) ( ) 120 on-resistance vs. v d and temperature (dual supplies) 100 dg406/7 toc-02 0 20 40 60 -15 15 -10 10 -5 5 0 80 v d (v) +125 c +85 c +25 c -55 c r ds (on) ( ) v+ = 15v v- = -15v 280 320 360 400 on-resistance vs. v d (single supply) 240 dg406/7 toc-03 40 80 120 160 15 20 10 5 0 200 v d (v) r ds (on) ( ) 5v 10v 15v 20v 120 140 160 on-resistance vs. v d and temperature (single supply) 100 dg406/7 toc-04 0 20 40 60 15 10 5 0 80 v d (v) r ds (on) ( ) +125 c +85 c +25 c -55 c v+ = 15vv- = 0v 30 charge injection vs. v d 20 dg406/7 toc-07 -30 -20 -10 0 -15 15 -10 10 -5 5 0 10 v d (v) q j (pc) v+ = 12v v- = 0v v+ = 15v v- = -15v 10 0.0001 -55 125 off leakage vs. temperature 1 dg406/7 toc-05 temperature ( c) off leakage (na) 25 0.01 0.001 -35 -15 65 0.1 100 1000 45 85 105 5 i no (off) i com (on) v+ = 15vv- = -15v 10 0.0001 -55 125 on leakage vs. temperature 1 dg406/7 toc-06 temperature ( c) on leakage (na) 25 0.01 0.001 -35 -15 65 0.1 100 1000 45 85 105 5 i com (on) v+ = 15vv- = -15v 100 0.001 -55 125 supply current vs. temperature 10 dg406/7 toc-08 temperature ( c) i+, i- ( a) 25 0.1 0.01 -35 -15 65 1 45 85 105 5 i+ i- v+ = +15vv- = -15v v en = v a = 0v, 4.5v __________________________________________typical operating characteristics (t a = +25?, unless otherwise noted.) downloaded from: http:///
__________applications information operation with supply voltages other than 15v using supply voltages other than ?5v reduces theanalog signal range. the dg406/dg407 switches oper- ate with ?.5v to ?0v bipolar supplies or with a +5v to +30v single supply; connect v- to gnd when operating with a single supply. also, both device types can oper- ate with unbalanced supplies such as +24v and -5v. the typical operating characteristics graphs show typical on-resistance with 20v, 15v, 10v, and 5vsupplies. (switching times increase by a factor of two or more for operation at 5v.) overvoltage protection proper power-supply sequencing is recommended forall cmos devices. do not exceed the absolute maxi- mum ratings because stresses beyond the listed rat- ings may cause permanent damage to the devices. always sequence v+ on first, then v-, followed by the logic inputs and analog signals. if power-supply sequencing is not possible, add two small signal diodes in series with supply pins for overvoltage pro- tection (figure 1). adding diodes reduces the analog signal range to 1v above v+ and 1v below v-, but lowswitch resistance and low leakage characteristics are unaffected. device operation is unchanged, and the difference between v+ and v- should not exceed +44v. dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers 6 _______________________________________________________________________________________ bidirectional output d 28 address inputs a3?0 14?7 enable inputs en 18 bidirectional analog inputs s1?8 19?6 negative supply voltage input v- 27 ground gnd 12 bidirectional analog inputs s16?9 4?1 dg406 pin no connection. not internally connected. n.c. 2, 3, 13 positive supply voltage input v+ 1 function name negative supply voltage input v- 27 bidirectional output a da 28 ground gnd 12 address inputs a2, a1, a0 15, 16, 17 enable input en 18 bidirectional analog inputs s1a?8a 19?6 bidirectional analog inputs s8b?1b 4?1 no connection. not internally connected. n.c. 3, 13, 14 dg407 pin bidirectional output b db 2 positive supply voltage input v+ 1 function name _____________________________________________________________pin descriptions v g s d v- v+ figure 1. overvoltage protection using external blocking diodes downloaded from: http:///
dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers _______________________________________________________________________________________ 7 ______________________________________________test circuits/timing diagrams 50% t trans t r < 20ns t f < 20ns v out +3v 0v v s1 0v v s16 logicinput switchoutput +15v v out -15v gnd v+ a1 v- a0 a2 a3 en s1 s2-s15 s16 d 10v +10v 50 dg406 300 35pf +15v v out -15v gnd v+ a1 v- a0 a2en s1b s1a-s8a s8b db 10v 50 dg407 300 35pf 90% 90% t trans on +10v 50% t off(en) t r < 20ns t f < 20ns v out +3v 0v0v logicinput switchoutput +15v v out -15v gnd v+ a1 v- a0 a2 a3 en s1 s2-s16 d -5v 50 dg406 1k 35pf 90% 10% t on(en) +15v v out -15v gnd v+ a1 v- a0 a2 en s1b s1a-s16a s2b-s16b, da db -5v 50 dg407 1k 35pf figure 2. transition time figure 3. enable switching time downloaded from: http:///
dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers 8 _______________________________________________________________________________________ 50% t open t r < 20ns t f < 20ns v out +3v 0v logicinput switchoutput +15v v out -15v gnd v+ a1 v- a0 a2 a3 en s1-s16 d +5v 50 dg406 300 35pf 80% +2.4v 0v v out +3v 0v logicinput +15v v out -15v gnd v+ a1 v- a0 a2 a3 en d dg406 c l = 1000nf v out s1-s16 channel select r s v s on off off v out is the measured voltage due to charge transfer error q when the channel turns off.q = c l = v out _________________________________test circuits/timing diagrams (continued) figure 4. break-before-make interval figure 5. charge injection downloaded from: http:///
dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers _______________________________________________________________________________________ 9 +15v v out -15v gnd v+ a1 v- a0 a2a3 s16 d dg406 s1 r s = 50 v in en 10nf r l = 1k off isolation = 20log v out v in 10nf +15v -15v gnd v+ a1 v- a0 a2a3 s16 com dg406 s2 r s = 50 v out en 10nf r l = 1k crosstalk = 20log v out v in 10nf s1 +15v -15v gnd v+ a2 v- a3a1 a0 s16 dg406 channel select s1 d en meter impedance analyzer f = 1mhz _________________________________test circuits/timing diagrams (continued) figure 6. off-isolation figure 7. crosstalk figure 8. source/drain capacitance downloaded from: http:///
dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers 10 ______________________________________________________________________________________ ________pin configurations/functional diagrams/truth tables (continued) 2827 26 25 24 23 22 21 12 3 4 5 6 7 8 dav- s8a s7a s6a s5a s4a s3a s2a s1a en a0 a1 a2 v+ db n.c. s8bs7b s6b s5b s4b s3b s2b s1b gnd n.c.n.c. top view 2019 18 17 9 1011 12 dip/so dg407 1615 1314 a2 a1 a0 en x 00 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x 00 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x 01 0 1 0 1 0 1 0 1 0 1 0 1 0 1 01 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 none 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 dg406 logic 0 v al 0.8v, logic 1 = v ah 2.4v a3 x 00 0 0 0 0 0 0 1 1 1 1 1 1 1 1 a2 a1 a0 en x 00 0 0 1 1 1 1 x 00 1 1 0 0 1 1 x 01 0 1 0 1 0 1 01 1 1 1 1 1 1 1 none 12 3 4 5 6 7 8 dg407 logic 0 v al 0.8v, logic 1 = v ah 2.4v s7bs6b s5b s4b s3b s2b s1b s7as6a s5a s4a s3a s2a s1a s8bn.c. db v+ da v- s8a gnd n.c.n.c. a2a1 a0 en plcc 12 13 14 15 16 17 18 1 2 3 4 26 27 28 19 20 21 22 23 24 25 56 7 8 9 10 11 dg407 n.c. = no internal connection downloaded from: http:///
dg406/dg407 cmos decoders/drivers a0 a1 a2 en s8b s7b s6b s5b s4b s3b s2b s1b s8a s7a s6a s5a s4a s3a s2a s1a da v+ v- gnd db dg407 8-channel differential multiplexer _ordering information (continued) * contact factory for dice specifications. + denotes a lead(pb)-free/rohs-compliant package. __functional diagrams (continued) part dg407 cj+ dg407cwi+ 0? to +70? 0? to +70? temp range pin-package 28 plastic dip 28 wide so dg407c/d+ 0? to +70? dice* dg407dj+ -40? to +85? 28 plastic dip dg407ewi+ -40? to +85? 28 wide so dg407dn+ -40? to +85? 28 plcc dg407ak -55? to +125? 28 cerdip dg407eui+ -40? to +85? 28 tssop improved, 16-channel/dual 8-channel, high-performance, cmos analog multiplexers ______________________________________________________________________________________ 11 package type package code document no. 28 pdip p28+3 21-0044 28 wide so w28+6 21-0042 28 plcc q28+4 21-0049 28 tssop u28+2 21-0066 28 cerdip j28+2 21-0046 package information for the latest package outline information and land patterns,go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. packagedrawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. downloaded from: http:///
dg406/dg407 improved, 16-channel/dual 8-channel, cmos analog multiplexers 12 ______________________________________________________________________________________ __________________________________________________________chip topographies gnd s1 s2 s3 s4 s5 s6 s7 s8 en a0 a1 a2 a3 n.c. 0.184" (4.67mm) 0.078" (1.98mm) s9 s10 s11 s12 s13 s14 s15 s16 n.c. v- d v+ gnd s1a s2a s3a s4a s5a s6a s7a s8a en a0 a1 a2 n.c. n.c. 0.184" (4.67mm) 0.078" (1.98mm) s1b s2b s3b s4b s5b s6b s7b s8b db v- da v+ substrate is internally connected to v+ substrate is internally connected to v+ dg406 dg407 n.c. = no internal connection downloaded from: http:///
dg406/dg407 improved, 16-channel/dual 8-channel, high-performance, cmos analog multiplexers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history reision number reision date description pages changed updated the minimum limit of the single suppl range. 1, 6 6 3/10 added the soldering temperature of all packages to the absolute maimum ratings . 2 downloaded from: http:///

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